錯誤更正碼暨積體電路設計實驗室是一個各方菁英一同研究的實驗室，由翁詠祿博士領導著研究生進行理論探討與IC實作。本實驗室位於台達館831室，已成功開發Wi-Fi、Flash memory、IEEE 802.15.3c等應用相關的錯誤更正編解碼技術，這些技術也獲得多件美國以及台灣專利，並技轉至國內的領導廠商。本實驗室研究成果豐碩，亦在眾多校內外競賽中獲得佳績，已畢業學長姐更充滿熱誠的投入相關的通訊以及IC設計產業。近年來也投入機器學習的相關應用。對通訊演算法與IC硬體設計或機器學習充滿熱忱的您，並不安於平凡、富熱情、渴望挑戰，更乞求學習成長的優秀青年學子，歡迎一同加入我們的研究行列。
Current research interests: Including Design of Error Correcting Codes(ECC), Quantum Error Correction Codes, Low-earth-orbit Satellite Communication Systems, High Frequency Trading(HFT), Prediction Methods of Stock Market Index, AI makeup.
With a focus on channel coding, we develop a variety of encoding and decoding algorithms designed to improve error-rate performances, including the construction of low-density parity-check (LDPC) codes, and the decoding algorithms for 5G polar codes, etc. We also investigate coded MIMO and massive MIMO systems. Multiple techniques have been devised that bring about considerable improvement for the entire communication system. In addition, we design good algorithms for use in channel decoders and MIMO detectors and are suitable for integrated circuit (IC) implementation in modern 6G/B5G communication systems.
Machine learning is a thriving field of electrical engineering and computer science that allows the computer to learn the structures of data without needing to be explicitly programmed. Many impressive applications have been identified in the field of machine learning, including image recognition, and artificial intelligence (AI), etc. Numerous projects relating to these fields are currently in progress in our lab. For example, machine-learning-aided decoding, which combines machine learning and channel coding to further improve the performance of traditional channel coding. Furthermore, one of our research projects, FinTech, includes time-series prediction functionality related to currencies and the stock market, etc.
ICs are the foundation of electronic products such as mobile phones and computers. The IC design group focuses on the VLSI designs for channel codecs (e.g. LDPC and Polar codecs) and MIMO transceivers for 5G/B5G systems. Communication algorithms and VLSI architectures are designed concurrently in order to optimize the chip performance. The associated training enables students to become professional IC designers who have the ability to both develop advanced hardware architecture and build a chip. Graduates will have a tremendous opportunity to join a leading IC design house such as MediaTek, Realtek, Silicon Motion, or Phison, etc.
Low-earth-orbit Satellite communication has become a trend when it comes to 6G/B5G system design, while LEO satellite is a possible and reliable solution for the purpose of wide-area coverage and high throughput communications, etc. The key challenges in LEO satellite systems including limited link budget in Space-earth transmission, severe carrier frequency offset due to highspeed doppler shift, consideration of hardware complexity and power consumption issues when deploying on LEO payload.